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This can occur simply because the engineer who designed the board may not sync with the FPGA designer who wrote the HDL. Net Naming ChallengesĪs mentioned in the introduction, it is common to find PCB designs using net names for FPGA IOs that don’t match the actual names in the FPGA HDL. This article will review some common pitfalls and ways to overcome those challenges when incorporating FPGAs into your PCB design project. As more users experiment with the FPGA Pin Mapper tool in Altium Designer, they will discover that the naming convention used in Altium Designer schematics may not always be legal in the FPGA design realm. As a result, there can often be a mismatch between PCB net names and the actual FPGA signal names. The naming convention used in Altium Designer schematics doesn’t always meet these criteria specified by the hardware description languages (HDL). It is a well-known fact that FPGA IO names must meet specific syntax requirements in Verilog or VHDL.